The present invention relates to an SOS (Silicon On Sapphire) wafer corresponding to one wafer for manufacturing a semiconductor device, and its manufacturing method.
In a conventional SOS wafer, a silicon layer and an oxide layer are laminated over the front surface of a sapphire substrate of the SOS wafer. A polysilicon layer having non-transparency and an electrical characteristic and a silicon nitride layer which protects the polysilicon layer are provided over the back surface of the sapphire substrate, thereby enabling optical and electrical detection of the SOS wafer.
Such an SOS wafer is formed by a conventional manufacturing method shown in FIG. 9.
The conventional method for manufacturing the SOS wafer will be explained below in accordance with processes or process steps indicated by PZ using FIG. 9. Incidentally, FIG. 9 shows partial sections of the SOS wafer.
In PZ1, an SOS wafer 5 is prepared in which a silicon layer 3 and an oxide layer 4 comprised of silicon dioxide are laminated over a front surface 2 of a sapphire substrate 1.
Such a normal SOS wafer 5 is of a circular wafer having a diameter of 125 mm. The thickness of the sapphire substrate 1 is 640 μm, the thickness of the silicon layer 3 is 1000 Å, and the thickness of the oxide layer 4 is about 3600 Å.
Incidentally, the diameter and shape of the SOS wafer 5 are not limited to the above. The SOS wafer 5 may be a wafer having other dimensions and shape.
In PZ2, a 2.3 μm-thick polysilicon layer 7 is formed on the back surface 6 of the sapphire substrate 1 by using low-pressure chemical vapor deposition (LPCVD). Since the polysilicon layer 7 is grown using the low-pressure chemical vapor deposition in the present process step, a polysilicon layer 7 is similarly formed even on the front surface 2 side.
Incidentally, the drawing indicative of the present process step is shown with its obverse and reverse sides placed in reverse relationship to the drawing indicative of the process step PZ1. The front surface 2 side is not illustrated (the drawings indicative of the process steps of the prior art shown below are also same).
In PZ3, ions of an impurity such as phosphorus (P) are implanted in the corresponding polysilicon layer 7 to form a conductive diffusion region 8. This implantation is carried out to obtain conductivity of a silicon wafer in such a manner that an electrical sensor of a silicon wafer processing apparatus designed so as to detect the silicon wafer, based on the conductivity of the wafer is capable of detecting the SOS wafer 5.
The ions implanted in the present process step are P+ (atomic weight: 31), a dose thereof is 1×1016/CM2, and implantation energy is 175 keV. The amount of diffusion of the impurity into the polysilicon layer 7 on the back surface 6 side is determined depending on the dose of the phosphorus. The implantation energy can also be reduced to 25 keV or so.
After the implantation of the phosphorus, resistivity of the conductive diffusion region 8 is normally set to less than approximately 50 Ω/square. This is because when the resistivity is set to 50 Ω/square or more, the resistivity becomes excessively high to allow the silicon wafer processing apparatus to detect the SOS wafer 5 as the silicon wafer on the basis of its conductivity.
In PZ4, a 900 Å-thick silicon nitride layer 9 is formed on the polysilicon layers 7 on the front surface 2 side of the sapphire substrate 1 and on the back surface 6 side thereof.
The silicon nitride layer 9 is used as a protection layer for protecting the polysilicon layers 7 and the conductive diffusion region 8 during subsequent processing of the SOS wafer 5.
Incidentally, the thickness of the silicon nitride layer 9 may be set to a range from about 500 Å to about 5000 Å. The thickness of the silicon nitride layer 9 is selected so as to sufficiently protect the polysilicon layer 7 and the like from subsequent processing applied to the SOS wafer 5.
The shape of each edge portion 10 of the SOS wafer 5 formed in this way is shown in FIG. 10. Incidentally, FIG. 10 shows the front surface 2 side of the sapphire substrate 1 with being turned upward in a manner similar to the drawing indicative of the process step PZ1.
As shown in FIG. 10, the edge portion 10 of the SOS wafer 5 is covered with the polysilicon layer 7 and the silicon nitride layer 9. Although these layers are placed on the edge portions 10, they are unnecessary according to the preferred embodiment of the prior art.
Since the ion implantation is effected only on the back surface 6, although the front surface 2 side of the sapphire substrate 1 is also covered with the polysilicon layer 7 and the silicon nitride layer 9, the region like the conductive diffusion region 8 on which the ion implantation is effected, does not exist in the polysilicon layer 7 that covers the front surface 2 side and the edge portion 10.
The silicon nitride layer 9 and the polysilicon layer 7 formed on the front surface 2 side of the sapphire substrate 1 according to the process steps PZ2 and PZ4 are removed by reactive ion etching so that the lower oxide layer 4 is exposed. Processing of the SOS wafer 5 placed in this state by the silicon wafer processing apparatus is enabled.
In the SOS wafer 5 formed in this way, the polysilicon layer 7 formed on the back surface 6 side of the sapphire substrate 1 is non-transparent enough to detect the existence of the SOS wafer 5 by a photosensor. The thickness of the polysilicon layer 7 is the suitable minimum thickness based on an indirect bandgap absorption method, enough to detect a non-transparent object by the photosensor.
Incidentally, it is necessary to change the thickness of the polysilicon layer 7 to be grown, according to a photosensor system employed in the silicon wafer processing apparatus. It is also necessary to change it even depending upon the wavelength of used light. Red light and infrared radiation are used in the current silicon wafer processing apparatus and enough to optically detect the existence of the SOS wafer 5 according to the thickness of the polysilicon layer 7 on the back surface 6 side. When light of other wavelength is used, the thickness of the polysilicon layer 7 may be set to such a thickness that the SOS wafer 5 can be detected as a silicon wafer, according to the photosensor employed in the silicon wafer processing apparatus.
Further, in the SOS wafer 5 formed in the above-described manner, the conductive diffusion region 8 having conductivity obtained by ion-implanting phosphorus into the polysilicon layer 7 is formed on the back surface 6 side.
The manufacturing method of the prior art does not form such a contamination level or defect density as to exert an influence on yield on the front surface 2 side of the SOS wafer 5, in addition to the fact that optical characteristics and conductive characteristics are made equivalent to the silicon wafer.
The films formed on the back surface 6 side of the SOS wafer 5 are adapted to a subsequent silicon processing process. This adaptability is obtained according to the selection of the films and the order of deposition of their films. That is, the polysilicon layer 7 and the silicon nitride layer 9 are adapted to all subsequent heat treatments.
Further, the silicon nitride layer 9 corresponding to the outer film serves as a diffusion barrier which prevents the silicon layer 3 on the front surface 2 side of the SOS wafer 5 from being auto-doped with an impurity implanted in the back surface 6 side by diffusion thereof through the surface of nitride. Further, the silicon nitride layer 9 corresponding to the outer film is inert to all acids except for phosphoric acid at a high temperature, and the phosphoric acid is not used even in any step.
A conventional SOS wafer has been manufactured by such a manufacturing method as described above (refer to, for example, a patent document 1 (Japanese Patent No. 3083725 (paragraph 0011 in page 3—paragraph 0016 in page 4, and FIGS. 1 through 5)).
There is known, as a technique for preventing warpage of an SOS wafer, one which forms a polysilicon layer in a back surface of a sapphire substrate and pulls back its warpage produced by a silicon layer on its front surface by virtue of the polysilicon layer formed in the back surface (refer to, for example, Japanese Unexamined Patent Publication No. Sho 57(1982)-153445 (lower right-hand section in page 2 and FIG. 2)).
There is also known a technique which thins a polysilicon layer to prevent warpage of an SOS wafer (refer to, for example, Japanese Unexamined Patent Publication No. 2000-36585 (paragraph 0015 in page 3 and FIG. 1)).
However, the technique of the patent document 1 referred to above is accompanied by problems that since silicon nitride layers are formed by low-pressure chemical vapor deposition, and the silicon nitride layer on the front surface side of a sapphire substrate is removed and the silicon nitride layer is provided so as to exist only in its back surface side, when they are used in processing of a silicon wafer processing apparatus, the front surface of the sapphire substrate is warped into convexity due to very large tensile stress developed in the silicon nitride layer formed by the low-pressure chemical vapor deposition, thus causing a failure in wafer vacuum chuck on the back surface side and a failure in transfer due to the warpage in a subsequent processing process of a semiconductor device, instability in a processing process for temperature ununiformity or the like at heat treatment, cracks of the SOS wafer, etc.